This invention relates to semiconductor devices, and more particularly to metal interconnections for semiconductor integrated circuits.
In the manufacture of VLSI devices, usually a thin metal coating such as aluminum is deposited and patterned to create interconnections. The shrinking dimensions of VLSI devices such as the 1-Megabit dynamic RAMs, requiring one micron sized geometries or less, creates fundamental problems with forming good low resistance, high-current metal interconnects. That is, when the width of a metal interconnect line is decreased as necessary in submicron geometries, the thickness of the metal must increase to maintain a given current capacity. But increased thickness is detrimental from a process standpoint due to the metal etch leaving filaments, and due to the step coverage problems for any subsequent layers, such as in a multiple-level metallization scheme.
It is the principal object of this invention to provide an improved process for making metal interconnections for semiconductor integrated circuits. Another object is to provide improved semiconductor devices with micron or submicron sized metallization patterns, avoiding high resistance or low current capability, and also avoiding process-related problems such as lack of planarity and unwanted filaments. A further object is to provide improved planarity and lower resistance for metallization patterns of semiconductor devices. Another object is to provide a method of making contacts that allow smaller pitch for the metal pattern (closer spacing between metal lines); thus higher density VLSI devices are possible.